The present invention relates generally to designs of integrated circuits (ICs), and, more particularly, to input circuit designs of the ICs.
With the advent of sub-micron technology, device dimensions in an IC chip are getting ever smaller to gain on speed and cost. At the same time, an operating voltage of the IC chip has also to be scaled down to accommodate the shrinking dimensions, such as thinner oxides and narrower spaces. However, on a board level, signal travel to and from the IC chip still in traditional high voltages for inter-operability with other chips and for maintaining signal integrity in a much noisier board level communication. For instance, a chip in a 90 nm technology may have an internal operating voltage of 1.0 V, yet it may interface with other devices on a 2.5 V level. For such an IC chip, its input buffer must transform the high board level voltage to the low chip level voltage.
However, the board level voltage may be unstable, and given these damage-prone, small geometry devices in the IC chip, there is a need to put protection devices in front of the input buffers to dampen an accidental high input signal voltage.
FIG. 1 is schematic diagram illustrating a conventional high-voltage-tolerant input buffer protection circuit 100, which comprises a NMOS transistor 110 coupled between a pad 120 and an input buffer 130. A gate of the NMOS transistor 110 is coupled to a chip peripheral power supply voltage (VDDP) to keep the NMOS transistor 110 to be always “on”. An electrostatic discharge (ESD) circuit 140 may be coupled between the NMOS transistor 110 and the pad 120 to prevent ESD damages to the NMOS transistor 110 as well as the input buffer 130 which may include an input regulating circuit 132 and a level-down converter 136. The input regulating circuit 132 receives a high voltage input signal from the pad 120, and transfers the high voltage input signal to a voltage level of either a ground (GND) or the VDDP. The level down converter 136 converts the VDDP voltage level to a chip core power supply voltage (VDD) level. The VDD is typically lower than VDDP.
When a signal voltage at the pad 120 is higher than the VDDP, the NMOS transistor 110 serves to drop some voltage across its source and drain, and to make a voltage at the input buffer 130 to be within a tolerable level.
However, when the IC chip is operated at lowered power supply environment, i.e., both the power supply VDDP and input voltage at pads are lowered, the voltage drop across the NMOS 110 further lowers the voltage received by the input buffer 130. In such lowered power supply environment, the voltage drop across the NMOS 110 may become so significant as it is compared to the input voltage at the pads that the voltage received by the input buffer 130 may approaching the threshold voltage thereof. Then the input buffer 130 may fail to operate correctly.
Such lowered power supply environment is quite common and often unpredictable in many silicon-on-chip (SOC) applications. In the SOC application, different ICs with different power supply voltages are merged in the same chip. To save the fabrication cost, a single design (e.g. circuit with 3.3V I/O devices) should be suitable for operating in different power-supply voltages (e.g., 3.3V, 2.5V, and 1.8V). Besides, for low-power design, the same IC may be operated at a lower power supply voltage during a power-saving mode. Then the conventional input buffer protection circuit 100 poses a reliability issue for the IC chip.
As such, what is desired is an input buffer protection circuit that can tolerate high voltage input as well as operate at lower-power supply voltages.